1769-L32C

描述

1769-L32C

FPGA获取并缓存四个视频源的数据流。这些FIFO缓冲器由DDR3存储器控制器清空并保存在DDR3存储器中。一旦一个完整的视频数据包存储完毕，视频处理器会向DDR3存储器控制器申请数据，存储器控制器读取数据并将其传到视频处理器。视频处理器对视频数据进行格式化和压缩，并通过DDR3存储器控制器写回存储器。当一个视频数据包全部处理完毕，并准备通过PCIExpress接口进行传输，DDR3存储器控制器从视频处理器获取数据并将其传到PCIExpress接口。DDR3存储器接口控制器概述从零开始设计一个DDR3存储器控制器是非常困难的。需要考虑许多特性之间的权衡和互相影响。使用一个经验证的IP核可以省去了大量的开发、测试和调试时间，否则就需要花费许多时间来进行in-house设计开发。一个经验证的IP核还可以减少后续支持的负担，因为这将由专门的开发人员来支持。最重要的是，使用一个经验证的IP核可以使设计师将精力集中在其设计的独特特性上，从而向最终客户交付高价值的产品设计。例如，LatticeECP3DDR3存储器控制器IP核已经通过了一个第三方验证套件的验证。该IP核使用LatticeECP3I/O协议板来实现并通过全部测试。展示了一个存储器控制器的框图。图最上面的配置接口用于设置设计的各个选项。DDR3I/O模块使用I/O基元来实现。指令译码模块根据每个bank和每一行，对用户指令进行译码，产生内部存储器指令序列。指令应用模块将每条指令序列转换为满足目标存储器件功能和时序要求的存储器指令。数据通路模块与DDR3I/O模块连接，并且在读操作时产生读数据和读取数据有效信号。读数据偏移校正模块对齐每一条8位数据线上的数据，调整任何可能的时钟偏移。这使得用户端的读数据总线与系统时钟准确校准。写调整模块为了正确的捕获数据，调整了DQS对CK的关系。ODT块通过为任意或所有DDR3SDRAM器件提供单独的终端阻抗控制，提高了存储器通道的信号完整性。

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